Error correction circuit employing cyclic code

ABSTRACT

An error correction circuit employing the cyclic code quickly corrects a single error contained in a received codeword. A serial-to-parallel converter converts the received codeword from serial data to parallel data. A CRC calculator divides the received codeword by a generator polynomial to output the remainder to logical gates. The logical gates determine to which of the remainder patterns, previously calculated for each location of the received codeword containing a single error, in which a single error is located, correspond to the remainder patterns output from the CRC calculator, and detects a location containing the single error. The logical gates set detection signals corresponding to the single error location to 1. An exclusive OR gate executes an exclusive OR operation on the received codeword output from the serial-to-parallel converter and the detection signal output from the logical circuits, on the bit basis, to correct the single error contained in the received codeword.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an error correction circuitemploying a cyclic code.

[0003] 2. Description of the Background Art

[0004] The signal transmitted over a transmission channel containserrors frequently. Among known methods for detecting such errors, thereis a CRC (cyclic redundancy check) error detection method, employing acyclic code. This error detection method detects code errors in afashion read as follows: With a received polynomial Y x), a generatorpolynomial G(x), a remainder polynomial S(x), a code polynomial W(x) andan error polynomial E(x), the remainder S(x), obtained on dividing Y(x)by G(x), is

S(x)=Y(x) mod G(x).   (1)

[0005] Supposing the degree of the polynomial G(x) is m or less, thedegree of the polynomial S(x) is (m−1) or less. SinceY(x)={W(x)+E(x)},the expression (1) may be rewritten to the followingform.

S(x)={W(x)+E(x)} mod G(x)   (2)

[0006] Since W(x) is generated so as to be completely divisible by G(x),the expression (2) may be rewritten to the following form.

S(x)=E(x) mod G(x)  (3)

[0007] The remainder polynomial S(x), termed a syndrome polynomial, isnot affected by the code polynomial W(x) but is determined solely by theerror polynomial E(x), as may be understood from the expression (3). Forerror detection, it is sufficient to check whether or not the polynomialS(x) calculated on a received codeword is coincident with the polynomialS(x) previously calculated on an error-free codeword. For errorcorrection, it is sufficient that the polynomial S(x) calculated on areceived codeword is compared with the polynomial S(x) previouslycalculated on a codeword for each degree containing an error to identifythe degree in which an error has occurred to correct the error.

[0008] Heretofore, in an error correcting circuit of a radiocommunication equipment, disclosed in e.g. Japanese patent laid-openpublication No. 221718/1995, the remainders for received codes,corrupted with errors, are calculated at the outset, the results ofremainder calculations and bit locations indicating the error locationsare provided in the form of table data, the results of remaindercalculations coincident with those calculated for actually receivedcodes are retrieved from the table data and the bit of the error bitlocation corresponding to the coincident results of remaindercalculations is corrected.

[0009] This error correction circuit is primarily aimed to find theerror bit location, and the received code is corrected for error basedon the error bit location of the received code specified using tabledata. Thus, the error correction circuit suffers from a problem that thecircuit is not efficient in an application in which the primary objectis to correct the error. It is because the bit position data indicatingthe error bit location is not particularly required in a case wherecorrection of the received code is the primary object.

[0010] Moreover, the above-described conventional error correctioncircuit suffers from a problem that the operation of locating an errorbit of the received code is time-consuming since it is necessary tocompare the remainder data obtained on remainder calculations of thereceived code using the generator polynomial sequentially with theresults of the remainder calculations of the table data. Since the tabledata are composed of the results from the remainder calculations for thetotality of the codes upon one-bit errors, the table data becomevoluminous when the length of the received code is increased. Forexample, if the code length of a received code is 196 bits, 196 entriesin the table data are needed, such that the operation of sequentialcomparison with the table data becomes extremely time-consuming.

SUMMARY OF THE INVENTION

[0011] It is an object of the present invention to provide an errorcorrection circuit employing the cyclic code in which theabove-described shortcomings of the related art may be overcome and thetime needed for error correction may be reduced appreciably.

[0012] For accomplishing the above object, the present inventionprovides an error correction circuit of the cyclic code systemcomprising a CRC calculator for calculating the remainder of a receivedcodeword in accordance with the CRC system, an error location detectorfor detecting the location of a single error contained in the receivedcodeword, based on a first remainder pattern calculated by the CRCcalculator, and an error bit corrector for correcting a bit of thereceived codeword, lying at a location detected by the error locationdetector.

[0013] In accordance with the present invention, there is provided theCRC calculator and the error location detector for detecting the errorposition by checking the syndrome in the case of a single error. Whenthe CRC calculator finds out the syndrome, the error location detectorcan detect the error location corresponding to the syndrome extremelyreadily, so that error correction can be executed speedily.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The objects and features of the present invention will becomemore apparent from consideration of the following detailed descriptiontaken in conjunction with the accompanying drawings in which:

[0015]FIG. 1 is a block diagram schematically showing a preferredembodiment of an error correction circuit according to the presentinvention;

[0016]FIG. 2 shows the bit array of the (7,4) Hamming code;

[0017]FIG. 3 is a schematic block diagram showing an example of a CRCcalculator in the error correction circuit of FIG. 1; and

[0018]FIG. 4 shows the remainder output from the CRC calculator in theerror correction circuit of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0019] With reference to FIG. 1, a preferred embodiment of the errorcorrection circuit employing the cyclic code according to the presentinvention is explained in detail. This error correction circuit shows anexample in which a received signal 100 is of the (7,4) Hamming code. Thecorrection circuit includes a CRC calculator 10, a serial-to-parallelconverter 12, logical gates 14-1 to 14-7, registers 16-1 to 16-7 andexclusive OR gates 18-1 to 18-7. It is noted that symbols affixed toconnection lines indicate signals present on the connection lines.

[0020] A received codeword 100 is of (7,4) Hamming code. FIG. 2 showsthe (7,4) Hamming code that is made up by information bits (bits 1 to 4)and check bits (bits 5 to 7). The received codeword 100 is seriallyinput to the CRC calculator 10 and to the serial to parallel converter12 in the order of from bit 1 to bit 7. If the received code 100 is inthe form of parallel data, it is sufficient to provide aparallel-to-serial converter, converting the parallel data to serialdata, on an input side of the error correction circuit, and to input anoutput of this parallel-to-serial converter to the CRC calculator 10 andto the serial-to-parallel converter 12.

[0021] The CRC calculator 10 is adapted for calculating the remainder ofthe received codeword 100 in accordance with the CRC system.Specifically, the CRC calculator is implemented by a division circuitfor dividing a received polynomial Y (x), which represents the receivedcodeword 100, by a cubic generator polynomial G (x) (=x³+x+1) to outputsignals 102, 104 and 106 that represent remainder of the division.

[0022]FIG. 3 is a block diagram showing an illustrative structure of theCRC calculator 10. This CRC calculator 10 is a routine division circuit,made up by exclusive OR gates 20 and 24 and flip-flops 22, 26 and 28.When a received codeword 120 is input to the exclusive OR gate 20, theflip-flop 28 outputs a quotient of division. At a time point when thelast bit of the received codeword 120 is input to the exclusive OR gate20, the calculations in the exclusive OR gates 20 and 24 are finishedand the flip-flops 22, 26 and 28 are updated, the contents R1, R2 and R3of the flip-flops 22, 26 and 28 represent the remainder of the division.

[0023]FIG. 4 shows values of R1 to R3 when an error-free receivedcodeword 100 or a received codeword 100 containing an error in one ofbits 1 to 7 is input to the CRC calculator 10. Meanwhile, [ALL 1] and[ALL 0] in FIG. 4 denote values of R1 to R3 when the initial values offlip-flops in the CRC calculator 10 corresponding to the flip-flops 22,26, 28 of FIG. 3 are all set to binary 1 and 0, respectively. Forexample, if the initial values are ALL 1, the values (R1, R2, R3) forthe received codeword 100 containing an error in the bit 1 are (0, 1,0).

[0024] Meanwhile, the values R1 to R3 represent coefficients of aremainder polynomial S(x). The remainder polynomial S(x) is theremainder obtained when an error polynomial E(x) is divided by thedivision circuit of FIG. 3, as may be seen from the above expression(3), and represents a remainder for an error polynomial E (x) containinga single error. In the case of a code with a Hamming distance of notless than 3, the remainder in the case a single error is contained in acertain degree is necessarily different from the remainder when a singleerror is contained in another degree. In FIG. 4, a set of values (R1,R2, R3) differs from one error location to another. Thus, if theremainder is found in advance for each error location, an error locationcorresponding to the remainder of the input received codeword can beidentified extremely readily.

[0025] The logical gates 14-1 to 14-7, connected to the CRC calculator10, form pattern detection circuits for detecting the patterns (R1, R2,R3) by executing logical operations on signals 102, 104 and 106 outputfrom the CRC calculator 10. The patterns detected are prefixed from onelogical gate to another. For example, the logical gates 14-1 and 14-2detect the patterns (0, 1, 0) and (0, 0, 0), respectively. In this case,the error location in the received codeword 100 has a one-to-onecorrespondence with the patterns, such that a group of the logical gates14-1 to 14-7 may be said to be an error location detector for detectingthe error location in the received codeword 100.

[0026] The logical gates 14-1 to 14-7 output the detected results in theform of detected signals 108-1 to 108-7. In the present embodiment, eachof the detected signals 108-1 to 108-7 is set to 1 or 0 when the patternhas been detected or not, respectively. In the embodiment, the logicalgates 14-1 to 14-7 are specifically adapted to detect the patterns of(R1, R2, R3) when the flip-flops in the CRC calculator 10 are set to 1.

[0027] The registers 16-1 to 16-7, connected to the logical gates 14-1to 14-7, respectively, contain flip-flops for temporarily holding thedetected signals 108-1 to 108-7 output from the logical gates 14-1 to14-7, and set the outputs 110-1 to 110-7 thereof to 1 or 0 when thedetected signals 108-1 to 108-7 are 1 or 0, respectively. Theserial-to-parallel converter 12 converts the received codeword 100 fromserial data to parallel data to store in its internal register, notshown, and outputs bits 1 to 7 of the parallel data stored in theinternal register, at the timing as commanded by a controller, also notshown, as signals 112-1 to 112-7, respectively.

[0028] The exclusive OR gates 18-1 to 18-7 have one input terminalconnected to the serial-to-parallel converter 12, and the other inputterminals thereof connected to the registers 16-1 to 16-7. The exclusiveOR gates 18-1 to 18-7 correct error bits contained in the receivedcodeword 100, and perform the exclusive OR operation on both signals112-1 to 112-7 output from the serial-to-parallel converter 12 andsignals 110-1 to 110-7 output from the registers 16-1 to 16-7 on thebit-by-bit basis, respectively.

[0029] For example, when an output 110-1 of the register 16-1 is 1, theexclusive OR gate 18-1 converts the output signal 112-1 of theserial-to-parallel converter 12 to 0 if the output signal 112-1 is 1,while converting the output signal 112-1 of the serial-to-parallelconverter 12 to 1 if the output signal 112-1 is 0, and outputs theresulting signal, by way of error correction. However, when the output110-1 of the register 16-1 is 0, the exclusive OR gate 18-1 outputs thesignal 112-1 uncorrected. The remaining exclusive OR gates 18-2 to 18-7operate in a similar manner. Thus, the exclusive OR gates 18-1 to 18-7correct the bits of the error locations detected by the logical circuits14-1 to 14-7, respectively. A group of the exclusive OR circuits 18-2 to18-7 may be said to be an error bit corrector for correcting an errorbit of the received codeword 100.

[0030] The error correction circuit of FIG. 1 operates as follows: Thereceived codeword 100 is input to the CRC calculator 10 and to theserial-to-parallel converter 12. The serial-to-parallel converter 12converts the received codeword 100, with a code length of 7 bits, fromserial data to parallel data, and holds the resulting parallel datatemporarily in its internal register. The serial-to-parallel converter12 then outputs bits 1 to 7 of the received codeword 100, thus held, assignals 112-1 to 112-7, respectively. The signals 112-1 to 112-7 areinput to the exclusive OR gates 18-1 to 18-7, respectively.

[0031] The CRC calculator 10 performs division on the received codeword100 and, at a time point when the last bit of the received codeword 100is input, outputs signals 102, 104, 106. The signals 102 to 106 arecorresponding to R1 to R3 representing the remainder of division.Meanwhile, the patterns of R1 to R3 (R1, R2, R3) differ in dependenceupon the location of the single error in the received codeword 100, asshown in FIG. 4. The signals 102 to 106 are input to the logical gates14-1 to 14-7 in parallel.

[0032] The logical gates 14-1 to 14-7 execute logical operations, basedon the signals 102, 104, 106, to detect the possible presence of thepatterns (R1, R2, R3) that are defined specifically to the logicalgates. If an error is contained in the n-th bit of the received codeword100, where 1≦n≦7, the logical gate 14-n sets an output detection signal108-n to 1, with the remaining logical gates setting the outputdetection signal outputs thereof to 0. If no error is contained in thereceived codeword 100, the entire logical circuits 14-1 to 14-7 setdetection signals 108-1 to 108-7 to 0. The detection signals 108-1 to108-7 are input to the registers 16-1 to 16-7.

[0033] The registers 16-1 to 16-7 temporarily hold the detection signals108-1 to 108-7, output from the logical gates 14-1 to 14-7, to outputthe detection signals, thus held, as signals 110-1 to 110-7. When thedetection signals 108-1 to 108-7 are 1 or 0, the signals 110-1 to 110-7become 1 or 0, respectively. The signals 110-1 to 110-7 and the signals112-1 to 112-7, output from the serial-to-parallel converter 12, areinput to the exclusive OR gates 18-1 to 18-7, respectively, in timedrelation to each other. The exclusive OR gates 18-1 to 18-7 perform theexclusive OR operation on both the signals 112-1 to 112-7 and thesignals 110-1 to 110-7, on the bit-by-bit basis, to output the resultsof the operations as signals 114-1 to 114-7, respectively.

[0034] For example, if the received codeword 100, containing an error inthe n-th bit, is input to the CRC calculator 10, the logical gate 14-ndetects the pattern (R1, R2, R3) in the case of an error existing in then-th bit, and sets the detection signal 108-n to 1, so that the outputsignal 110-n of the register 16-n is 1. The signal 110-n and the signal112-n, which is the n-th bit of the received codeword 100 are input tothe exclusive OR gate 18-n. Since the signal 110-n is 1, the exclusiveOR gate 18-n corrects the signal 112-n to 0 or to 1, when the signal112-n is 1 or 0, respectively, to output the resulting signal 114-n.

[0035] At this time, the logical gates other than the logical gate 14-nset the detection signals to 0. Thus, the output signals of theregisters other than the register 16-n are all 0. Consequently, theexclusive OR gates other than the exclusive OR gate 18-n directly outputthe signals input from the serial-to-parallel converter 12. In thismanner, the exclusive OR gates 18-1 to 18-7 correct errors contained inthe received codeword 100 to output a corrected codeword 114 composed ofthe signals 114-1 to 114-7.

[0036] Although the present embodiment is directed to an errorcorrection circuit employing the (7,4) Hamming code, the presentinvention may also be applied to any other cyclic code in which theHamming distance is not less than 3. The present invention may, ofcourse, be applied to such a case where the generator polynomial is a16-bit generator polynomial recommended by the CCITT (Comit ConsultatifInternationale Telegraphique et Telephonique). On the other hand, whenthe Hamming distance is not less than 5, double errors may also becorrected, to which case the present embodiment may be applied.

[0037] Moreover, when the received codeword 100 contains a single error,(R1, R2, R3), calculated by the CRC calculating unit 10, falls under oneof (R1, R2, R3) shown in FIG. 4. However, if the received codeword 100contains plural bit errors, a set of values (R1, R2, R3), calculated bythe CRC calculating unit 10, does not fall under any of the (R1, R2, R3)shown in FIG. 4. Thus, by detecting whether or not the set of values(R1, R2, R3), calculated by the CRC calculating unit 10, falls under the(R1, R2, R3) shown in FIG. 4, it is possible to verify whether or notthe error is of two or more bit errors.

[0038] The entire disclosure of Japanese patent application No.2002-339659 filed on Nov. 22, 2002, including the specification, claims,accompanying drawings and abstract of the disclosure is incorporatedherein by reference in its entirety.

[0039] While the present invention has been described with reference tothe particular illustrative embodiment, it is not to be restricted bythe embodiment. It is to be appreciated that those skilled in the artcan change or modify the embodiment without departing from the scope andspirit of the present invention.

What is claimed is:
 1. An error correction circuit, employing a cycliccode, comprising: a CRC calculator for calculating a remainder of areceived codeword in accordance with a CRC system; an error locationdetector for detecting a location of a single error contained in thereceived codeword, based on a first remainder pattern calculated by saidCRC calculator; and an error bit corrector for correcting a bit of thereceived codeword, lying at a location detected by said error locationdetector.
 2. The error correction circuit in accordance with claim 1,wherein said error location detector determines to which of secondremainder patterns, previously calculated for each location of thereceived codeword containing a single error, in which the single erroris located, correspond to said first remainder pattern.
 3. The errorcorrection circuit in accordance with claim 2, wherein said errorlocation detector includes a plurality of logical circuits for detectingpatterns corresponding to the second remainder patterns according to thesecond remainder patterns to output detection signals; and said logicalcircuits set the detection signals to binary 1 or 0 on detecting acorresponding pattern or on not detecting a corresponding pattern,respectively.
 4. The error corrector in accordance with claim 3, whereinsaid error bit correction circuit includes a plurality of exclusive ORcircuits executing exclusive OR operations on the detection signalsoutput from said logical circuits and bits of the received codeword foreach bit of the received codeword.